Power Conversion Devices and Control Methods Therefor

ABSTRACT

Power conversion devices with control algorithms that can solve the double frequency harmonic problem are provided, as are techniques for controlling power converters when the instantaneous values of input and output power are not the same.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 §119(e) of U.S. ProvisionalApplication No. 62/338,103, filed on May 18, 2016, entitled “SparseCapacitive Link Power Converter and Control Method Therefor,” thedisclosure of which is hereby incorporated by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

N/A

BACKGROUND

The growing dependency on renewable energy sources and the wide range ofelectrical loads in residential and industrial applications, demands thenext generation of power electronics circuits to be more flexible andcapable of transferring electrical power from any types of source,including dc, single-phase ac, or multi-phase ac, to any type of load(dc, single-phase ac, or multi-phase ac) without compromisingreliability, cost, efficiency, or power density. There are numerousapplications in which the instantaneous values of input and output powerare not equal. For instance, in a single-phase inverter the inputcurrent and voltage are ideally both dc, resulting in a constant dcpower; whereas, the load power has a dc component and an alternatingcomponent the frequency of which is twice the frequency of the loadvoltage/current. The alternating part of the load power will result inthe appearance of a double frequency current harmonic at the dc-side, ifit is not suppressed. The presence of double frequency harmoniccomponent at the dc-side current is undesirable and can deteriorate theperformance of the system. Similarly, in a single-phase ac tosingle-phase ac converter, the instantaneous values of input and outputpower will not be the same if the input and output frequencies do notmatch. Moreover, the instantaneous power of a three-phase system will bedc; therefore interfacing a single-phase system and a three-phase acsystem will also results in the appearance of the double frequencyharmonic.

The most dominant solution for suppressing the double frequency harmonicis filtering it through a large (high capacitance) capacitor.Electrolytic capacitors are available at high capacitances; however,they have very high failure rates, and are considered the leading causeof failures in power electronic circuits. The failure rates of the othertypes of capacitors, i.e. film and ceramic capacitors, are much lowerthan that of electrolytic capacitors; however, they are not available athigh capacitances.

SUMMARY OF THE INVENTION

The invention relates to power converters with control algorithms thatcan solve the double frequency harmonic problem and to techniques forcontrolling power converters when the instantaneous values of input andoutput power are not the same.

In some embodiments, single phase inverters/rectifiers havingconfigurations as well as control schemes that solve the doublefrequency harmonic problem without using electrolytic capacitors oradding any additional components to the circuit.

In some embodiments, a single phase inverter is provided that cantransfer power from input towards output through a small capacitorplaced in series with input and output switch bridges. This capacitorcan suppress the double frequency harmonic of the single phase inverterwithout affecting input or output currents/voltages. The voltage of thiscapacitor has a large ripple, because it has very low capacitance.However, its large voltage ripple does not deteriorate the performanceof the inverter. The small link capacitance allows using film capacitorsinstead of electrolytic capacitors. In a further embodiment, an inverteris also provided that uses a parallel capacitor for transferring thepower.

In some embodiments, an inverter based on a buck-boost converter isprovided that can transfer power from the source toward the load througha small inductor. As with the previous embodiments, this inductor canregulate input and output currents while suppressing the doublefrequency harmonic.

In some embodiments, power converters with control algorithms areprovided that can solve the double frequency harmonic problem in dc tosingle-phase ac, single-phase ac-to-single-phase ac, and single-phase acto three-phase ac converters without using electrolytic capacitors oradding any additional components to the circuit. In some embodiments,the techniques can be used in any system that has unequal instantaneousinput and output power values.

In some embodiments, a class of converters uses a small link capacitor(series or parallel) for transferring the power from input towardsoutput. This capacitor can manage the mismatch of input and outputpower, as well. For instance, it can suppress the double frequencyharmonic of the single phase inverter without affecting input or outputcurrents/voltages. The voltage of this capacitor may have larger voltageripple, because it has very low capacitance. However, its large voltageripple does not deteriorate the performance of the inverter. The smalllink capacitance allows using film capacitors instead of electrolyticcapacitors.

In some embodiments, a class of converters transfers power from a sourcetowards a load through a small inductor. This inductor regulates theinput and output currents while managing the mismatch of instantaneousinput and output power values. No additional passive components arerequired in the proposed converters for eliminating the double frequencyharmonic.

Further aspects include the following:

-   1. A power conversion device comprising:

input circuitry configured to be coupled to a power source or load, theinput circuitry comprising at least one switching device or diode;

an output switch bridge configured to be coupled to a load or powersource, the output switch bridge comprising at least four controllableswitching devices arranged in a bridge configuration to control currentoutput; and

a link stage comprising at least one reactive component configured foralternating current (AC) operation, wherein the input circuitry, outputswitch bridge and link stage are operative to regulate input and outputcurrents and manage power mismatch between the power source and load.

-   2. The device of embodiment 1, wherein the device is operative to    suppress a double frequency harmonic component at the input    circuitry.-   3. The device of any of embodiments 1-2, wherein switches in the    input circuitry and output switch bridge are operative at a fixed    switching frequency.-   4. The device of any of embodiments 1-3, wherein the device is    operative in a discontinuous current mode.-   5. The device of any of embodiments 1-4, wherein the device is    operative to control the input current to be about equal to a    selected reference value.-   6. The device of any of embodiments 1-5, wherein the input circuitry    comprises an input switch bridge configured to be coupled to a    direct current (DC) power source, the input switch bridge comprising    at least one switching device controllable to regulate an input DC    current with suppression of a double frequency harmonic component;    and the output switch bridge is configured to be coupled to an AC    load, the output switch bridge comprising at least four controllable    switching devices arranged in a bridge configuration to control    current output to the load.-   7. The device of embodiment 6, wherein the input switch bridge    comprises at least a second switching device, and the input switch    bridge is configured to be coupled to a second direct current (DC)    power source.-   8. The device of embodiments 6, wherein the input switch bridge    comprises at least four switching devices arranged in a bridge    configuration.-   9. The device of any of embodiments 1-8, wherein the device is    operative as a single phase inverter or rectifier.-   10. The device of any of embodiments 1-9, wherein the device is    operative to regulate the input current and the output current    simultaneously.-   11. The device of any of embodiments 1-10, wherein the link stage is    arranged in series or in parallel with the input switch bridge and    the output switch bridge.-   12. The device of any of embodiments 1-11, wherein the reactive    component comprises at least one capacitive device having an    operative range of about 1×10⁻⁴ F to less than 1×10⁻⁹ F.-   13. The device of any of embodiments 1-12, wherein the reactive    component comprises a film capacitor, a ceramic capacitor, or an    electrolytic capacitor.-   14. The device of any of embodiments 1-13, wherein the reactive    component comprises an inductive device.-   15. The device of any of embodiments 1-14, wherein the at least one    reactive component comprises a galvanic isolation device.-   16. The device of any of embodiments 1-15, wherein the device is    operative to provide bidirectional flow of power.-   17. The device of any of embodiments 1-16, wherein the output switch    bridge is configured to be coupled to a second load.-   18. The device of any of embodiments 1-17, wherein the input    circuitry is coupled to an AC power source or load.-   19. The device of any of embodiments 1-18, wherein the input    circuitry is coupled to a single phase AC source or load.-   20. The device of any of embodiments 1-19, wherein the output switch    bridge is coupled to an AC load or power source.-   21. The device of any of embodiments 1-20, wherein the output switch    bridge is coupled to a single phase, three phase, or poly phase AC    load or source.-   22. The device of any of embodiments 1-21, wherein each of the    switching devices of the output switch bridge comprises a field    effect transistor (FET), an insulated gate bipolar transistor    (IGBT), or a metal-oxide-semiconductor field-effect transistor    (MOSFET) with anti-parallel diode.-   23. The device of any of embodiments 1-22, wherein the at least one    the switching device of the input circuitry comprises a field effect    transistor (FET), an insulated gate bipolar transistor (IGBT), or a    metal-oxide-semiconductor field-effect transistor (MOSFET) with    anti-parallel diode.-   24. The device of any of embodiments 1-23, further comprising    circuitry that causes, and/or a controller comprising one or more    processors, memory, and machine-readable instructions stored in the    memory that, upon execution by the one or more processors, cause the    device to carry out operations to control sequence and duration of    each of the controllable switching devices.-   25. The device of any of embodiments 1-24, wherein the device is    operative in at least three states, including at least one state to    charge the reactive component of the link stage from the power    sources and through the input switch bridge, at least one state in    which power is discharged from the link stage into the loads through    the output switch bridge, and at least one state in which no power    is transferred through the link stage.-   26. The device of any of embodiments 1-25, wherein a voltage rating    of the switching devices is about equal to a maximum link stage    voltage.-   27. The device of any of embodiments 1-26, wherein a maximum voltage    of the link stage is selected based on a selected maximum link stage    capacitance.-   28. The device of any of embodiments 1-27,wherein the link stage    comprises a plurality of capacitors, each capacitor in series with a    bidirectional conducting bidirectional blocking controllable    switching device, the plurality of capacitors arranged in series or    in parallel with the input circuitry and the output switch bridge.-   29. The device of embodiment 28, wherein each capacitor transfers    power in at least two switching cycles over a load power cycle.-   30. The device of any of embodiments 1-29, further comprising a    transformer connected to an AC load or AC source.-   31. The device of any of embodiments 1-26 and 30, wherein the link    stage comprises a plurality of series inductors, each inductor in    parallel with a forward conducting bidirectional blocking    controllable switching device, the plurality of inductors arranged    in series or in parallel with the input circuitry and the output    switch bridge.-   32. A method of controlling a power conversion device, comprising:

providing the power conversion device of embodiment 1; and

operating the device to regulate the input and output currents withsuppression of a double frequency harmonic component.

-   33. The method of embodiment 32, further comprising operating the    device in a first state to charge the reactive component of the link    stage from the input switch bridge, in a second state in which power    is discharged from the link stage into the output switch bridge, and    in a third state in which no power is transferred through the link    stage.-   34. A method of controlling a power conversion device, comprising:

providing the power conversion device of embodiment 1; and

operating the device with a plurality of switching cycle, each switchingcycle comprising at least one charging state, at least one dischargingstate, and at least one state during which no power is transferred.

DESCRIPTION OF THE DRAWINGS

The invention will be more fully understood from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIG. 1 is a circuit diagram of an embodiment of a bidirectionalsingle-phase capacitive link inverter with series link (dc

single-phase ac);

FIG. 2 is a circuit diagram of an embodiment of a bidirectionalsingle-phase capacitive link inverter with parallel link (dc

single-phase ac);

FIG. 3 is a circuit diagram of an embodiment of a dc-to-single phase accapacitive link converter with series link (dc=>single-phase ac);

FIG. 4 is a circuit diagram of an embodiment of a single-phase ac-to-dccapacitive link converter with series link (single-phase ac=>dc);

FIG. 5 is a circuit diagram of an embodiment of a dc-to-single phase accapacitive link converter with parallel link (dc=>single-phase ac);

FIG. 6 is a circuit diagram of an embodiment of a single-phase ac-to-dccapacitive link converter with parallel link (single-phase ac=>dc);

FIG. 7 is a circuit diagram of an embodiment of a bidirectionalsingle-phase capacitive link inverter with galvanic isolation;

FIG. 8 is a circuit diagram of an embodiment of a multi-port capacitivelink-converter with series link;

FIG. 9 is a circuit diagram of an embodiment of a multi-port capacitivelink-converter with parallel link;

FIG. 10 illustrates in panels (a), (b), and (c) circuit diagramsillustrating principles of the operation of an embodiment of abidirectional single-phase capacitive link inverter with series linkwhen power flows from dc-side to ac-side and load current (I_ac) ispositive;

FIG. 11 illustrates in panels (a), (b), and (c) circuit diagramsillustrating principles of the operation of a bidirectional single-phasecapacitive link inverter with series link when power flows from ac-sideto dc-side and load current (I_ac) is positive;

FIG. 12 illustrates in panels (a), (b), and (c) circuit diagramsillustrating principles of operation of a bidirectional single-phasecapacitive link inverter with parallel link when power flows fromdc-side to ac-side and load current (I_ac) is positive;

FIG. 13 illustrates in panels (a), (b), and (c) circuit diagramsillustrating principles of operation of a bidirectional single-phasecapacitive link inverter with parallel link when power flows fromac-side to dc-side and load current (I_ac) is positive;

FIG. 14 is a graph illustrating inherent double frequency harmonic insingle phase inverters;

FIG. 15 is a graph illustrating link voltage and current of abidirectional single-phase capacitive link inverter when theinstantaneous source power is higher than the instantaneous load power;

FIG. 16 is a graph illustrating link voltage and current of abidirectional single-phase capacitive link inverter when theinstantaneous source power is lower than the instantaneous load power;

FIG. 17 is a graph illustrating low frequency component of the link in abidirectional single-phase capacitive link inverter;

FIG. 18 is a graph illustrating maximum value of link capacitance vs.selected minimum value of the link voltage (V₁(0)) for a 1 kW system

$\left( {{V_{m} = {200\mspace{14mu} V}},{I_{m} = {10\mspace{14mu} A}},{V_{dc} = {50\mspace{14mu} V}},{I_{dc} = {20\mspace{14mu} A}},{f_{s} = {6\mspace{14mu} {kHz}}},{f_{o} = {60\mspace{14mu} {Hz}}},{\theta_{V} = {- \frac{\pi}{4}}},{{{and}\mspace{14mu} \theta_{i}} = {- \frac{\pi}{4}}},} \right);$

FIG. 19 is a graph illustrating maximum value of link voltage vs.selected minimum value of the link voltage (V₁(0)) for a 1 kW system

$\left( {{V_{m} = {200\mspace{14mu} V}},{I_{m} = {10\mspace{14mu} A}},{V_{dc} = {50\mspace{14mu} V}},{I_{dc} = {20\mspace{14mu} A}},{f_{s} = {6\mspace{14mu} {kHz}}},{f_{o} = {60\mspace{14mu} {Hz}}},{\theta_{V} = {- \frac{\pi}{4}}},{{{and}\mspace{14mu} \theta_{i}} = {- \frac{\pi}{4}}},} \right);$

FIG. 20 is a circuit diagram of an embodiment of a bidirectionalsingle-phase capacitive link inverter using a series capacitor network(dc

single-phase ac);

FIG. 21 is a circuit diagram of an embodiment of a bidirectionalsingle-phase capacitive link inverter using a parallel capacitor network(dc

single-phase ac);

FIG. 22 is a graph illustrating input and output power and the voltageacross each capacitor when

$\frac{f_{s}}{4\; f_{o}}$

number of capacitors are used in the proposed single-phase capacitivelink inverter;

FIG. 23 is a graph illustrating the voltage across an arbitrarycapacitor when

$\frac{f_{s}}{4\; f_{o}}$

number of capacitors are used in the proposed single-phase capacitivelink inverter;

FIG. 24 is a graph illustrating the voltage across an arbitrarycapacitor (x^(th) capacitor) when an optional number of capacitors areused in a single-phase capacitive link inverter;

FIG. 25 is a graph illustrating maximum voltage across theswitches/diodes vs. the number of capacitors used in as a capacitornetwork in a single-phase capacitive link inverter for a 1 kW system

$\left( {{V_{m} = {200\mspace{14mu} V}},{I_{m} = {10\mspace{14mu} A}},{V_{dc} = {50\mspace{14mu} V}},{I_{dc} = {20\mspace{14mu} A}},{f_{s} = {6\mspace{14mu} {kHz}}},{f_{o} = {60\mspace{14mu} {Hz}}},{\theta_{V} = {- \frac{\pi}{4}}},{\theta_{i} = {- \frac{\pi}{4}}},{C = {2.2\mspace{14mu} {µF}}}} \right);$

FIG. 26 is a circuit diagram of an embodiment of a bidirectionalsingle-phase ac-to-three-phase ac capacitive link converter with serieslink (single-phase ac

three-phase ac);

FIG. 27 is a circuit diagram of an embodiment of a bidirectionalsingle-phase ac-to-three-phase ac capacitive link converter withparallel link (single-phase ac

three-phase ac);

FIG. 28 is a circuit diagram of an embodiment of a bidirectionalsingle-phase ac-to-three-phase ac capacitive link converter withgalvanic isolation (single-phase ac

three-phase ac);

FIG. 29 illustrates in panels (a), (b), (c), and (d) circuit diagramsillustrating principles of the operation of a bidirectional single-phaseac-to-three-phase ac capacitive link converter with series link whenpower flows from single-phase ac side to three-phase ac side;

FIG. 30 illustrates in panels (a), (b), (c), and (d) circuit diagramsillustrating principles of the operation of a bidirectional single-phaseac-to-three-phase ac capacitive link converter with parallel link whenpower flows from single-phase ac side to three-phase ac side;

FIG. 31 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to three-phase ac capacitive linkconverter using a series capacitor network (single-phase ac

three-phase ac);

FIG. 32 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to three-phase ac capacitive linkconverter using a parallel capacitor network (single-phase ac

three-phase ac);

FIG. 33 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to single-phase ac capacitive linkconverter with a series link (single-phase ac

single-phase ac);

FIG. 34 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to single-phase ac capacitive linkconverter with a parallel link (single-phase ac

single-phase ac);

FIG. 35 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to single-phase ac capacitive linkconverter with galvanic isolation (single-phase ac

single-phase ac);

FIG. 36 is a graph illustrating low frequency component of the linkvoltage in a single-phase ac to single-phase ac capacitive linkconverter for a 1 kW system with f_(i)=60 Hz and f₀=120 Hz;

FIG. 37 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to single-phase ac capacitive linkconverter using a series capacitor network (single-phase ac

single-phase ac);

FIG. 38 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to single-phase ac capacitive linkconverter using a parallel capacitor network (single-phase ac

single-phase ac);

FIG. 39 is a circuit diagram illustrating an embodiment of abidirectional single-phase inductive-link inverter for positive dc-sidecurrent (dc<=>single-phase ac);

FIG. 40 is a circuit diagram illustrating an embodiment of abidirectional single-phase inductive-link inverter for positive andnegative dc-side currents (dc

single-phase ac);

FIG. 41 is a circuit diagram illustrating an embodiment of abidirectional single-phase inductive-link inverter for positive dc-sidecurrent with galvanic isolation (dc<=>single-phase ac);

FIG. 42 is a circuit diagram illustrating an embodiment of abidirectional single-phase inductive-link inverter for positive andnegative dc-side currents with galvanic isolation (dc

single-phase ac);

FIG. 43 is a circuit diagram illustrating an embodiment of a multi-portsingle-phase inductive-link inverter;

FIG. 44 illustrates in panels (a), (b), and (c) circuit diagramsillustrating principles of operation of a single-phase inductive-linkinverter;

FIG. 45 is a graph illustrating link inductor current in a single-phaseinductive-link inverter;

FIG. 46 is a circuit diagram illustrating an embodiment of asingle-phase inductive-link inverter with inductor network;

FIG. 47 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to three-phase ac inductive-link converter(single-phase ac

three-phase ac);

FIG. 48 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to three-phase ac inductive-link converterwith galvanic isolation (single-phase ac

three-phase ac);

FIG. 49 illustrates in panels (a), (b), (c), and (d) circuit diagramsillustrating principles of operation of a bidirectional single-phase acto three-phase ac inductive-link converter;

FIG. 50 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to three-phase ac inductive-link converterwith inductor network (single-phase ac

three-phase ac);

FIG. 51 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to single-phase ac inductive-linkconverter (single-phase ac

single-phase ac);

FIG. 52 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to single-phase ac inductive-linkconverter with galvanic isolation (single-phase ac

single-phase ac);

FIG. 53 is a circuit diagram illustrating an embodiment of abidirectional single-phase ac to single-phase ac inductive-linkconverter with inductor network (single-phase ac

single-phase ac).

DETAILED DESCRIPTION OF THE INVENTION

This application incorporates by reference the entire disclosure of U.S.Provisional Application No. 62/338,103, filed on May 18, 2016, entitled“Sparse Capacitive Link Power Converter and Control Method Therefor.”

The invention relates to embodiments of power conversion devices havingconfigurations as well as control schemes that regulate input and outputcurrents and manage input and output power mismatches. Some embodimentsare operable to suppress dc-side double frequency harmonic components.Some embodiments can operate without using electrolytic capacitors.

In some embodiments, a power conversion device includes input circuitryconfigured to be coupled to a power source or load, and having at leastone switching device or diode. An output switch bridge is configured tobe coupled to a load or power source, the output switch bridge having atleast four controllable switching devices arranged in a bridgeconfiguration to control current output. A link stage includes at leastone reactive component configured for alternating current (AC) operationand is operative to manage input and output of power mismatch betweenthe input circuitry and the output switch bridge.

In some embodiments, a power conversion device employs an additionalswitch, operates in discontinuous conduction mode (DCM), and uses fixedswitching frequency. These features allow this inverter to suppress thedouble frequency harmonic. In some embodiments, the power conversiondevice includes an input switch bridge configured to be coupled to adirect current (DC) power source. The input switch bridge includes atleast one switching device controllable to regulate an input DC currentwith suppression of a double frequency harmonic component. A link stageincludes at least one reactive component configured for alternatingcurrent (AC) operation. The device includes an output switch bridgeconfigured to be coupled to an AC load. The output switch bridgeincludes at least four controllable switching devices arranged in abridge configuration to control current output to the load.

1. Capacitive-Link Converters

1.1 Capacitive-Link Inverter (dc

Single-Phase ac)

FIG. 1 shows an embodiment of a capacitive-link inverter 10 having afirst topology that is used for interfacing a dc source (or load) 11 anda single-phase ac load (or source) 17. This bidirectional inverter issingle-stage, and transfers power from input towards output through thelink capacitor (C) 14, which is placed in series with the input switch12 and the output switch bridge 16. As shown in FIG. 2, the linkcapacitor 14′ can also be placed in parallel with the input switch 12′and output switch-bridge 16′ while changing the polarity of theoutput-side switches. In FIGS. 1 and 2 the dc-side voltage is positive(top terminal has positive voltage); however, the dc-side current can bepositive (from left to right) or negative (from right to left).Depending on the polarity of the dc-side current the power can flow fromdc-side towards ac-side or from ac-side towards dc side. Forunidirectional power flow from dc-side to ac-side or from ac-side todc-side, a switch and/or a diode can be eliminated from each of thesetopologies, as shown in FIGS. 3-6.

In some embodiments, of converters, galvanic isolation can be providedby a high frequency transformer 15 added to the link 14″, as shown inFIG. 7. In some embodiments, this inverter is capable of interfacingseveral sources (DC1, DC2, . . . DCn) and loads (AC1, AC2, . . . ACm) asdepicted in FIGS. 8 and 9.

1.1.1 Principles of Operation of the Bidirectional Capacitive-LinkInverter

Regardless of the direction of the power flow, this converter has threestates (mode) in each switching cycle. FIG. 10 shows the behavior of thefirst topology when the power flows from dc side to the ac side.

1) State 1—charging the link capacitor through the source: during thisstate, switch S0 is off. If the load current (I_ac) is positive (rightto left), switch S4 and diodes D3 and D1 provide paths for input andoutput currents. If the load current is negative, switch S3 and diodesD2 and D4 are conducting. During this state, the link current is equalto the dc-side current and it is positive. Therefore, the voltage acrossthe link increases.

2) State 2—discharging the link capacitor into the load: during thisstate, switch S0 is on to provide a path for the input current and theload current. Switches S1 and S4, if the load current is positive, andswitches S2 and S3, if the load current is negative, provide a path forthe load current. During this state, the magnitude of the link currentis equal to that of the output current and its polarity is negative.Therefore, the voltage across the link decreases.

3) State 3—no power transfer: during this state switch S0 is on toprovide a path for input current. If the load current is positive,switch S4 and diode D3 provides a path for the load current. If loadcurrent is negative switch S3 and diode D4 are conducting instead of S4and D3. During this state the link current is zero, and the link voltageremains constant.

Duration of state 1 is determined such that input current meets itsreference, and duration of state 2 is controlled such that the loadcurrent meets its reference. State 3 is needed due to the mismatch ofinput and output power, and its duration depends on the differencebetween input and output power. In this manner, double frequencyharmonic components can be suppressed.

The behavior of the first topology when the power flows from the ac sideto the dc side is shown in FIG. 11. In this figure it is assumed I_ac ispositive. As seen in this figure, during the first state, diodes D2 andD3 allow I_ac to charge the link capacitor while D0 provides a path fordc-side current and ac-side current. In the second state, dc-sidecurrent discharges the link capacitor, and switches S1 and S4 conduct.If the ac-side current is higher than the dc-side current, D3 conducts;otherwise, S3 conducts. During the third state link current is zero, anddiodes D0 and D3 along with switch S4 provide paths for the dc-side andac-side currents. If I_ac is negative D1 and D4 conduct instead of D2and D3 during the 1st state. In the second state S2 and S3 along with S4or D4, depending on the values of dc-side and ac-side currents, conductwhile in the thirds state D0, S3 and D4 conduct, if I_ac is negative.

The behavior of the second proposed topology (parallel link) when thepower flows from dc-side to the ac-side is depicted in FIG. 12. In thisfigure I_ac is assumed to be positive. Similar to the first proposedtopology, there are three states:

1) State 1—charging the link capacitor through dc source: during thisstate, diode D1 conducts to allow the dc-side current to charge the linkcapacitor while S4 and D5 provide a path for the ac-side current. IfI_ac is negative, S5 and D4 conduct instead of S4 and D5.

2) State 2—discharging the link capacitor into the load: during thismode switch S0 conducts to provide a path for dc-side current. SwitchesS4 and S3 conduct and allow the link capacitor to be discharged into theload. For negative values of I_ac S2 and S5 will conduct instead of S3and S4.

3) State 3—no power transfer: during this mode switches S0 and S4 alongwith diode D5 provide paths for the dc-side and ac-side currents. Fornegative values of I_ac, switches S0 and S5 along with diode D4 areconducting.

FIG. 13 depicts the behavior of the 2nd proposed topology when powertransfers from the ac-side to the dc-side assuming I_ac is positive.

1.1.2 Analysis of Capacitive-Link Inverter

The disclosed inverters are analyzed as follows, and the maximum voltageof the link capacitor as well as the required link capacitance aredetermined. The maximum voltage of the link capacitor determines thevoltage stress of the switches and diodes.

1.1.2.1 Voltage Rating of the Switches/Diodes

The output and input voltages and currents of a single-phase inverterare expressed in (1)-(4):

v _(o)(t)=V _(m) sin(ωt+θ _(V))=V _(m) sin(2πf _(o) t+θ _(V))   (1)

i _(o)(t)=I _(m) sin(ωt+θ _(I))=I _(m) sin(2πf _(o) t+θ _(I))   (2)

v _(in)(t)=V _(dc)   (3)

i _(in)(t)=I _(dc)   (4)

Using (1)-(4), the output power and the input power, shown in FIG. 14,can be calculated as follows:

$\begin{matrix}{{P_{o}(t)} = {{\frac{I_{m}V_{m}}{2}\left\{ {{\cos \left( {\theta_{V} - \theta_{I}} \right)} - {\cos \left( {{2\omega \; t} + \theta_{V} + \theta_{I}} \right)}} \right\}} = {\frac{I_{m}V_{m}}{2}\left\{ {{\cos \left( {\theta_{V} - \theta_{I}} \right)} - {\cos \left( {{4\pi \; f_{o}t} + \theta_{V} + \theta_{I}} \right)}} \right\}}}} & (5) \\{\mspace{79mu} {{P_{in}(t)} = {{V_{dc} \times I_{dc}} = {\frac{I_{m}V_{m}}{2}{\cos \left( {\theta_{V} - \theta_{I}} \right)}}}}} & (6)\end{matrix}$

According to (5), the instantaneous output power has a dc component andan alternating component the frequency of which is twice the outputvoltage/current frequency (f_(o)). The dc component of the output poweris equal to the input power. The mismatch of input and output powervalues need to be managed by the link capacitor. Therefore, theinstantaneous value of capacitor power is as follows:

$\begin{matrix}{{P_{c}(t)} = {{\frac{I_{m}V_{m}}{2}{\cos \left( {{2\omega \; t} + \theta_{V} + \theta_{I}} \right)}} = {\frac{I_{m}V_{m}}{2}{\cos \left( {{4\pi \; f_{o}t} + \theta_{V} + \theta_{I}} \right)}}}} & (7)\end{matrix}$

Assuming C, i_(c)(t), and v_(c)(t) are the link capacitance and lowfrequency components of the link capacitor current and voltage, thefollowing expression needs to be met:

$\begin{matrix}{{P_{c}(t)} = {{{v_{c}(t)} \times {i_{c}(t)}} = {C \times {v_{c}(t)} \times \frac{d\left( {v_{c}(t)} \right)}{dt}}}} & (8)\end{matrix}$

One of the possible solutions for (7) and (8) is as follows:

$\begin{matrix}{{{v_{c}(t)} = {\sqrt{\frac{I_{m}V_{m}}{C\; \omega}}{\sin \left( {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \right)}}}{0 \leq {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \leq \pi}} & (9) \\{{{v_{c}(t)} = {{- \sqrt{\frac{I_{m}V_{m}}{C\; \omega}}}{\sin \left( {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \right)}}}{\pi \leq {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \leq {2\pi}}} & (10) \\{{{i_{c}(t)} = {C\; \omega \sqrt{\frac{I_{m}V_{m}}{C\; \omega}}{\cos \left( {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \right)}}}{0 \leq {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \leq \pi}} & (11) \\{{{i_{c}(t)} = {{- C}\; \omega \sqrt{\frac{I_{m}V_{m}}{C\; \omega}}{\cos \left( {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \right)}}}{\omega \leq {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \leq {2\pi}}} & (12)\end{matrix}$

The above response results in having a minimum link voltage of zero. Itis also possible to determine the link capacitor voltage and currentsuch that the minimum voltage of capacitor is above zero. One possiblesolution for this case is as follows:

$\begin{matrix}{{v_{c}(t)} = \sqrt{{\frac{I_{m}V_{m}}{2\; C\; \omega}{\sin \left( {{2\omega \; t} + \theta_{V} + \theta_{I}} \right)}} + V_{0}}} & (13) \\{{i_{c}(t)} = \frac{I_{m}V_{m}{\cos \left( {{2\omega \; t} + \theta_{V} + \theta_{I}} \right)}}{2\sqrt{{\frac{I_{m}V_{m}}{2\; C\; \omega}{\sin \left( {{2\omega \; t} + \theta_{V} + \theta_{I}} \right)}} + V_{0}}}} & (14)\end{matrix}$

In prior art techniques, only (13) and (14) are considered as thevoltage and current across the link capacitor.

As mentioned earlier, in any switching cycle, there are three states.The voltage of the link capacitor at the beginning of states 1 to 3 inany arbitrary cycle (i^(th) cycle) is expressed as V₁(i), V₂(i), andV₃(i), respectively. During the first state (charging mode), the inputcurrent passes the link capacitor and charges the capacitor. Thisresults in an increase of the link voltage from V₁(i) to V₂(i). Duringthe second state (discharging mode), the load current passes the linkcapacitor. However, the current of the link capacitor during this state(discharging mode) is negative. This results in a decrease of the linkvoltage from V₂(i) to V₃(i). As shown in FIGS. 15 and 16, if theinstantaneous value of the input power is higher than the instantaneousvalue of the output power, V₃(i) will be higher than V₁(i); otherwise,V₃(i) will be lower than V₁(i). During the third state, no currentpasses the link capacitor, and the link voltage remains equal to V₃(i).The voltage at the beginning of the next cycle ((i+1)^(th) cycle) willbe equal to V₃(i):

V ₁(i+1)=V ₃(i)   (15)

If the input power is higher than the load power, V₁(i+1) will be higherthan V₁(i). Assuming f_(s) is the switching frequency, in each loadpower cycle, the duration of which is

$\frac{1}{2\; f_{o}},$

there are

$\frac{f_{s}}{2\; f_{o}}$

high frequency cycles. In half of these cycles the input power is higherthan the load power, and in another half of these cycles, the inputpower is lower than the load power. FIG. 17 shows the low frequencycomponent of the link capacitor voltage.

Assuming the duration modes 1 to 3 in i^(th) cycle are t₁(i), t₂(i), andt₃(i), respectively, (16) to (18) describe the behavior of the circuitduring the charging state of an arbitrary switching cycle (the i^(th)cycle, where

$\left. {1 \leq i \leq \frac{f_{s}}{2\; f_{o}}} \right):$

$\begin{matrix}{{i_{in}(i)} = {I_{dc} = {C\frac{{V_{2}(i)} - {V_{1}(i)}}{t_{1}(i)}}}} & (16) \\{{v_{in}(i)} = {V_{dc} = {{t_{1}(i)} \times f_{s}\frac{{V_{2}(i)} + {V_{1}(i)}}{2}}}} & (17) \\{{P_{in}(i)} = {{I_{dc}V_{dc}} = {{\frac{I_{m}V_{m}}{2}{\cos \left( {\theta_{V} - \theta_{I}} \right)}} = {\frac{1}{2}{{Cf}_{s}\left( {{V_{2}^{2}(i)} - {V_{1}^{2}(i)}} \right)}}}}} & (18)\end{matrix}$

The behavior of the converter during the discharging state can beexpressed through (19) to (21):

$\begin{matrix}{\mspace{79mu} {{i_{o}(i)} = {{I_{m}{\sin \left( {{\frac{2\pi \; f_{o}}{f_{s}}i} + \theta_{I}} \right)}} = {C\frac{{V_{2}(i)} - {V_{3}(i)}}{t_{2}(i)}}}}} & (19) \\{\mspace{79mu} {{v_{o}(i)} = {{V_{m}{\sin \left( {{\frac{2\pi \; f_{o}}{f_{s}}i} + \theta_{V}} \right)}} = {{t_{2}(i)} \times f_{s}\frac{{V_{2}(i)} + {V_{3}(i)}}{2}}}}} & (20) \\{{P_{o}(t)} = {{{v_{o}(i)}*{i_{o}(i)}} = {{\frac{I_{m}V_{m}}{2}\left\{ {{\cos \left( {\theta_{V} - \theta_{I}} \right)} - {\cos\left( {{\frac{4\pi \; f_{o}}{f_{s}}i} + \theta_{V} + \theta_{I}} \right)}} \right\}} = {{\frac{1}{2}{{Cf}_{s}\left( {{V_{2}^{2}(i)} - {V_{3}^{2}(i)}} \right)}} = {\frac{1}{2}{{Cf}_{s}\left( {{V_{2}^{2}(i)} - {V_{1}^{2}\left( {i + 1} \right)}} \right)}}}}}} & (21)\end{matrix}$

Using (18) and (21), V₁(i+1) can be calculated:

$\begin{matrix}{{{V_{1}^{2}\left( {i + 1} \right)} = {{\frac{I_{m}V_{m}}{{Cf}_{s}}{\cos \left( {{\frac{4\pi \; f_{o}}{f_{s}}i} + \theta_{V} + \theta_{I}} \right)}} + {V_{1}^{2}(i)}}}\left( {1 \leq i \leq \frac{f_{s}}{2\; f_{o}}} \right)} & (22)\end{matrix}$

Assuming the initial value of the link voltage across the link capacitoris V₁(0), (22) can be simplified as follows:

$\begin{matrix}{{V_{1}^{2}\left( {i + 1} \right)} = {{\sum\limits_{x = 1}^{i}\; \left( {\frac{I_{m}V_{m}}{{Cf}_{s}}{\cos \left( {{\frac{4\pi \; f_{o}}{f_{s}}x} + \theta_{V} + \theta_{I}} \right)}} \right)} + {V_{1}^{2}(0)}}} & (23)\end{matrix}$

The value of V₁(i+1) can be determined as follows:

$\begin{matrix}{{V_{1}\left( {i + 1} \right)} = \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\frac{{\sin \left( {\frac{2\pi \; f_{o}}{f_{s}} \times \left( {i + 1} \right)} \right)}{\cos \left( {{\frac{2\pi \; f_{o}}{f_{s}} \times i} + \theta_{V} + \theta_{I}} \right)}}{\sin \left( \frac{2\pi \; f_{o}}{f_{s}} \right)}} + {V_{1}^{2}(0)}}} & (24)\end{matrix}$

Using (24) and (18), V₂(i) can be determined:

$\begin{matrix}{{V_{2}(i)} = \sqrt{\begin{matrix}{{\frac{I_{m}V_{m}}{{Cf}_{s}}\frac{{\sin \left( {\frac{2\pi \; f_{o}}{f_{s}} \times \left( {i + 1} \right)} \right)}{\cos \left( {{\frac{2\pi \; f_{o}}{f_{s}} \times i} + \theta_{V} + \theta_{I}} \right)}}{\sin \left( \frac{2\pi \; f_{o}}{f_{s}} \right)}} +} \\{{\frac{I_{m}V_{m}}{{Cf}_{s}}{\cos \left( {\theta_{V} - \theta_{I}} \right)}} + {V_{1}^{2}(0)}}\end{matrix}}} & (25)\end{matrix}$

It can be shown that the maximum value of V₂ that occurs at

${= \frac{f_{s}}{4\; f_{o}}},$

and is equal to:

$\begin{matrix}{V_{2,\max} = \sqrt{{{- \frac{I_{m}V_{m}}{{Cf}_{s}}}\frac{{\cos \left( \frac{2\pi \; f_{o}}{f_{s}} \right)}{\sin \left( {\theta_{V} + \theta_{I}} \right)}}{\sin \left( \frac{2\pi \; f_{o}}{f_{s}} \right)}} + {\frac{I_{m}V_{m}}{{Cf}_{s}}{\cos \left( {\theta_{V} - \theta_{I}} \right)}} + {V_{1}^{2}(0)}}} & (26)\end{matrix}$

Assuming

${\theta_{V} = {\theta_{I} = {- \frac{\pi}{4}}}},$

the maximum value of V_(2 is) is as follows:

$\begin{matrix}{V_{2,\max} = \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\left( {\frac{\cos \left( \frac{2\pi \; f_{o}}{f_{s}} \right)}{\sin \left( \frac{2\pi \; f_{o}}{f_{s}} \right)} + 1} \right)} + {V_{1}^{2}(0)}}} & (27)\end{matrix}$

If f_(o)<<f_(s), the maximum value of V₂ can be determined by (28):

$\begin{matrix}\begin{matrix}{V_{2,\max} = {\sqrt{\frac{I_{m}V_{m}}{2\pi \; f_{o}C} + \frac{I_{m}V_{m}}{{Cf}_{s}} + {V_{1}^{2}(0)}} \cong \sqrt{\frac{I_{m}V_{m}}{2\pi \; f_{o}C} + {V_{1}^{2}(0)}}}}\end{matrix} & (28)\end{matrix}$

The voltage rating of all the switches and diodes in the disclosedinverters are equal to V_(2,max). It should be noted that although thevalue of V₁(0) is optional, it needs to be in the following range:

$\begin{matrix}{0 \leq {V_{1}(0)} \leq {\frac{V_{m}}{\sqrt{2}} + V_{o}}} & (29)\end{matrix}$

1.1.2.2 Maximum Capacitance

To make sure this inverter has all the three states in each switchingcycle, the following condition must be valid:

$\begin{matrix}{{{t_{1}(i)} + {t_{2}(i)}} < \frac{1}{f_{s}}} & (30)\end{matrix}$

Using (17) and (20), (30) can be written as follows:

$\begin{matrix}{{\frac{2V_{dc}}{{V_{2}(i)} + {V_{1}(i)}} + \frac{2{v_{o}(i)}}{{V_{2}(i)} + {V_{1}\left( {i + 1} \right)}}} < 1} & (31)\end{matrix}$

It can be shown that the maximum value of t₁(i)+t₂(i) occurs at

$i = {\frac{f_{s}}{2f_{o}}.}$

The values of V₂ and V₁ at this point can be calculated by (24) and(25):

$\begin{matrix}{{V_{1}\left( \frac{f_{s}}{2f_{o}} \right)} = {{V_{1}\left( {\frac{f_{s}}{2f_{o}} + 1} \right)} = \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\mspace{11mu} \cos \mspace{11mu} \left( {\theta_{V} + \theta_{I}} \right)} + {V_{1}^{2}(0)}}}} & (32) \\{{V_{2}\left( \frac{f_{s}}{2f_{in}} \right)} = \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\mspace{11mu} \cos \mspace{11mu} \left( {\theta_{V} + \theta_{I}} \right)} + {\frac{I_{m}V_{m}}{{Cf}_{s}}\mspace{11mu} \cos \mspace{11mu} \left( {\theta_{V} - \theta_{1}} \right)} + {V_{1}^{2}(0)}}} & (33)\end{matrix}$

Plugging (32) and (33) into (31) determines the maximum value of thelink capacitance:

$\begin{matrix}{{{{2V_{m}{\sin \left( {\pi + \theta_{V}} \right)}}} + {2V_{dc}}} < {\sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\mspace{11mu} \cos \mspace{11mu} \left( {\theta_{V} + \theta_{I}} \right)} + {V_{1}^{2}(0)}} + \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\mspace{11mu} \cos \mspace{11mu} \left( {\theta_{V} + \theta_{I}} \right)} + {\frac{I_{m}V_{m}}{{Cf}_{s}}\mspace{11mu} \cos \mspace{11mu} \left( {\theta_{V} - \theta_{1}} \right)} + {V_{1}^{2}(0)}}}} & (34)\end{matrix}$

Assuming

${\theta_{V} = {\theta_{I} = {- \frac{\pi}{4}}}},$

proper values of V₁(0), C, and f_(s) can be selected such that:

$\begin{matrix}{{{V_{m}\sqrt{2}} + {2V_{dc}}} < {\sqrt{\frac{I_{m}V_{m}}{{Cf}_{s}} + {V_{1}^{2}(0)}} + {V_{1}(0)}}} & (35)\end{matrix}$

The maximum value of the link capacitance will be as follows:

$\begin{matrix}{C < \frac{l_{m}V_{m}}{{f_{s}\left( {{V_{m}\sqrt{2}} + {2V_{dc}}} \right)}\left( {{V_{m}\sqrt{2}} + {2V_{dc}} - {2{V_{1}(0)}}} \right)}} & (36)\end{matrix}$

A unique feature of the disclosed inverter is that it does not have anyminimum requirement for the link capacitance; instead it has a maximumrequirement.

Plugging the maximum value of the capacitance achieved from (36) into(28), the voltage rating of the switches/diodes, which is equal to themaximum value of the link voltage, is determined as follows:

$\begin{matrix}{V_{2,\max} \cong \sqrt{\left( {\frac{f_{s}}{2\pi \; f_{o}}\left( {{V_{m}\sqrt{2}} + {2V_{dc}}} \right)\left( {{V_{m}\sqrt{2}} + {2V_{dc}} - {2{V_{1}(0)}}} \right)} \right) + {V_{1}^{2}(0)}}} & (37)\end{matrix}$

1.1.3 Techniques for Reducing the Voltage Rating of the Switches

According to (36) and (28), the link capacitance of the proposedinverter can be as small as the designer wishes; however, choosing avery small value for C increases the maximum value of the link voltage.Accordingly, a number of techniques for reducing the maximum value ofthe link voltage are described herein.

1.1.3.1 Choosing a Nonzero Value for Minimum Voltage of the LinkCapacitor to Increase the Maximum Capacitance

According to (36) and (28), choosing a nonzero value for V₁(0) helpsincrease the maximum value of the link capacitance and reduces thevoltage stress. The closer V₁(0) is to its maximum value (determined by(29)) the lower the peak voltage of the capacitor is. As an example,FIG. 18 shows the maximum value of link capacitance for different valuesof V₁(0), assuming

${V_{m} = {200\mspace{11mu} V}},{I_{m} = {10\mspace{11mu} A}},{V_{dc} = {{50}\mspace{11mu} V}},\; {I_{dc} = {20A}},{f_{s} = {6\mspace{11mu} {kHz}}},{f_{o} = {{60\mspace{11mu} {Hz}\mspace{11mu} \theta_{V}} = {- \frac{\pi}{4}}}},{{{and}\mspace{14mu} \theta_{i}} = {\frac{\pi}{4}.}}$

FIG. 19 depicts the maximum value of link voltage in this system fordifferent values of V₁(0), assuming the maximum link capacitance isselected.

1.1.3.2 Use of Multiple Capacitors (a Capacitor Network) for Reducingthe Voltage Rating of the Switches/Diodes

To minimize the voltage rating of the switches in the inverter, acapacitor network can be used instead of a single capacitor. Theschematics of the embodiment of an inverter when a capacitor network isused instead of a single capacitor are illustrated in FIGS. 20 and 21.

One approach is to use

$\frac{f_{s}}{4f_{o}}$

number of capacitors such that each capacitor can be involved intransferring the power in two switching cycles (cycle “i” and cycle

$\left. {\;^{''}\frac{f_{s}}{4f_{o}} + i^{''}} \right)$

over a load power cycle, the frequency of which is 2f_(o). Thedifference between the instantaneous values of the input power andoutput power in cycles “i” and

$\;^{''}\frac{f_{s}}{4f_{in}} + i^{''}$

are equal but they have opposite polarities. This implies that the netenergy is zero, and the voltage of the capacitor at the beginning ofcycle “i” is equal to the voltage of the capacitor at the end of cycle

${\;^{''}\frac{f_{s}}{4f_{o}}} + {i^{''}.}$

FIG. 22 shows this concept.

It is also possible to use an arbitrary number of capacitors. In thiscase each capacitor will be involved in transferring the power in morethan two switching cycles over a load power cycle, i.e. in i^(th) cycle,

$\;^{''}\frac{f_{s}}{4f_{o}} + i^{''{th}}$

cycle, and a number of consequent cycles after cycles i and

$\frac{f_{s}}{4f_{in}} + {i.}$

Both approaches are discussed below.

1.1.3.2.1 Using

$\frac{f_{s}}{4\; f_{0}}$

Number of Capacitors

FIG. 23 shows the voltage of an arbitrary capacitor (x^(th) capacitor)that transfers power in cycle x and cycle

$\frac{f_{s}}{4\; f_{in}} + x$

In cycle x the input power is higher than the load power; therefore,V_(c,x,3) (the voltage of x^(th) capacitor at the end of x^(th) cycle)will be higher than V_(c,x,1) (the voltage of x^(th) capacitor at thebeginning of x^(th) cycle). In cycle

$\frac{f_{s}}{4\; f_{in}} + x$

the input power is lower than the load power; thus, the voltage ofx^(th) capacitor at the beginning this cycle, which is equal toV_(c,x,3), will be higher than its voltage at the end of this cycle. Asmentioned earlier the difference between input and output power valuesare the same in these two cycles but they have opposite polarities. Thisimplies that the voltage of the capacitor at the end of cycle

$\frac{f_{s}}{4\; f_{in}} + x$

will be equal to V_(c,x,1).

The peak value of the voltage across x^(th) capacitor in each of the twocycles, i.e. cycles x and

${\frac{f_{s}}{4\; f_{in}} + x},$

can be determined based on V_(C,x,1) and the instantaneous values ofsource power and load power. The values of V_(C,x,2) and V_(C,x,4) canbe determined by (38) and (39):

$\begin{matrix}{C_{c,x,2} = \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}{\cos \left( {\theta_{V} - \theta_{I}} \right)}} + V_{C,x,1}^{2}}} & (38) \\{V_{c,x,4} = \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\left\{ {{\cos \left( {\theta_{V} - \theta_{I}} \right)} - {\cos \left( {{\frac{4\; \pi \; f_{o}}{f_{s}}i} + \theta_{V} + \theta_{I}} \right)}} \right\}} + V_{C,x,1}^{2}}} & (39)\end{matrix}$

Assuming

$\theta_{V} = {\theta_{I} = {{- \frac{\pi}{4}}\mspace{14mu} {and}}}$V_(c, x, 1) = 0, V_(C, x, 2  )and V_(C, x, 4  )

will be as follows:

$\begin{matrix}{V_{c,x,2} = \sqrt{\frac{I_{m}V_{m}}{{Cf}_{s}}}} & (40) \\{V_{c,x,4} = \sqrt{\frac{I_{m}V_{m}}{{Cf}_{s}}\left\{ {1 + {\sin \left( {4\; \pi \frac{f_{o}}{f_{s}}x} \right)}} \right\}}} & (41)\end{matrix}$

According to (40), V_(C,x,2) does not depend on the value of x;therefore, the peak value of the voltage across all the capacitorsduring the first half cycle of the load power is the same. However, thevalue of V_(C,x,4) depends on the value of x. To find the voltage stressof the switches/diodes, the maximum value of V_(C,x,4) needs to bedetermined. It should be noted that

${1 < x < \frac{f_{s}}{4\; f_{o}}};$

therefore,

$0 < {\sin \left( {\frac{4\; \pi \; f_{in}}{f_{s}}x} \right)} < 1.$

This implies that V_(C,x,4) varies in the following range:

$\begin{matrix}{\sqrt{\frac{I_{m}V_{m}}{{Cf}_{s}}} < V_{C,x,4} < \sqrt{\frac{2I_{m}V_{m}}{{Cf}_{s}}}} & (42)\end{matrix}$

The voltage rating of the switches/diodes, which is equal to the maximumvalue of V_(c,x,4), is as follows:

$\begin{matrix}{V_{\max} = \sqrt{\frac{21_{m}V_{m}}{{Cf}_{s}}}} & (43)\end{matrix}$

If maximum value of capacitance, determined by (36), is used, themaximum value of the link voltage will be as follows:

V_(max)=2×(V_(m)+√{square root over (2)}V_(cd))   (44)

Assuming as an example

$\begin{matrix}{{V_{m} = {200\mspace{20mu} V}}{I_{m} = {10\mspace{14mu} A}}{{V_{dc} = {50\mspace{20mu} V}},{I_{dc} = {20\mspace{20mu} A}},{f_{s} = {6\mspace{14mu} {kHz}}},\; {f_{o} = {60\mspace{14mu} {Hz}}},{\theta_{V} = {- \frac{\pi}{4}}},{\mspace{11mu} \;}{and}}{{\theta_{i} = {- \frac{\pi}{4}}},}} & (43)\end{matrix}$

the maximum voltage stress of this inverter is 816V when 25 capacitorsare used.

1.1.3.2.2 Using an Arbitrary Number of Capacitors

As mentioned above, it is also possible to use each capacitor for morethan two cycles. The voltage of an arbitrary link capacitor (x^(th)capacitor) that transfers power during 2N switching cycles over the loadpower cycle is shown in FIG. 24. In this figure, the arbitrary capacitor(x^(th) capacitor) is involved in transferring the power in cycles(x−1)N+1 to xN and cycles

$\frac{f_{s}}{4\; f_{o}} + {\left( {x - 1} \right)N} + {1\mspace{14mu} {to}\mspace{14mu} \frac{f_{s}}{4\; f_{o}}} + {{xN}.}$

There are

$M = \frac{f_{s}}{4N\; f_{o}}$

number of capacitors in this inverter, and x varies in the followingrange:

$\begin{matrix}{1 \leq x \leq \frac{f_{s}}{4\; N\; f_{o}}} & (45)\end{matrix}$

During cycles (x−1)N+1 to xN, the input power is higher than the loadpower; therefore, the voltage across the capacitor at the end of eachcycle is higher than that of beginning of that cycle. During cycles

$\frac{f_{s}}{4\; f_{o}} + {\left( {x - 1} \right)N} + {1\mspace{14mu} {to}\mspace{14mu} \frac{f_{s}}{4\; f_{o}}} + {x\; N}$

the input power is lower than the output power; thus, the voltage of thecapacitor at the end of each cycle is lower than the beginning of thecycle.

The value of the link voltage at the beginning of each cycle(V_(C,x,2i+1)) depends on its value at the beginning of the previouscycle (V_(C,x,2i−1)) and the alternating part of the load power in thatcycle:

$\begin{matrix}{{\frac{l_{m}v_{m}}{2}{\cos \left( {{\frac{4\; \pi \; f_{o}}{f_{s}}\left( {{\left( {x - 1} \right)N} + i} \right)} + \theta_{V} + \theta_{I}} \right)}} = {{\frac{1}{2}{{Cf}_{s}\left( {V_{C,x,{{2i} + 1}}^{2} - V_{C,x,{{2i} - 1}}^{2}} \right)}\mspace{14mu} 1} \leq i \leq N}} & (46)\end{matrix}$

Assuming the initial voltage of the x^(th) capacitor is V_(C,x,1), thevoltage of this capacitor at the end of each cycle (cycle (x−1)N+i) canbe determined as follows:

$\begin{matrix}{V_{C,x,{{2i} + 1}} = \sqrt{{\sum\limits_{y = 1}^{i}\; \left( {\frac{I_{m}V_{m}}{{Cf}_{s}}{\cos \left( {{\frac{4\; \pi \; f_{o}}{fs}\left( {{\left( {x - 1} \right)N} + y} \right)} + \theta_{V} + \theta_{I}} \right)}} \right)} + V_{C,x,1}^{2}}} & (47)\end{matrix}$

The voltage of the capacitor at the end of (xN)^(th) cycle can bedetermined by (48):

$\begin{matrix}{V_{C,x,{{2N} + 1}} = \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\frac{{\sin \left( {\frac{4\pi \; f_{o}}{f_{s}} \times \frac{N + 1}{2}} \right)}{\cos \left( {{\frac{4\; \pi \; f_{o}}{f_{s}} \times \frac{N}{2}} + {\frac{4\; \pi \; f_{o}}{fs}\left( {x - 1} \right)N} + \theta_{V} + \theta_{I}} \right)}}{\sin \left( \frac{2\; \pi \; f_{o}}{fs} \right)}} + V_{C,x,1}^{2}}} & (48)\end{matrix}$

The peak value of the voltage across x^(th) capacitor occurs in cycle

${\frac{f_{s}}{4\; f_{o}} + {\left( {x - 1} \right)N} + 1},$

and it can be determined as follows:

$\begin{matrix}{V_{C,x,{{2N} + 2}} = \sqrt{{\frac{I_{m}V_{m}}{{Cf}_{s}}\frac{{\sin \left( {\frac{4\pi \; f_{o}}{f_{s}} \times \frac{N + 1}{2}} \right)}{\cos \left( {{\frac{4\; \pi \; f_{o}}{f_{s}} \times \frac{{2{xN}} - N}{2}} + \theta_{V} + \theta_{I}} \right)}}{\sin \left( \frac{2\; \pi \; f_{o}}{fs} \right)}} + {\frac{I_{m}V_{m}}{{Cf}_{s}}{\cos \left( {\theta_{V} - \theta_{I}} \right)}} + V_{C,x,1}^{2}}} & (49)\end{matrix}$

Assuming

${\theta_{V} = {\theta_{I} = {{{- \frac{\pi}{4}}\mspace{14mu} {and}\mspace{14mu} V_{c,x,1}} = 0}}},$

(49) can be simplified as follows:

$\begin{matrix}{V_{C,x,{{2N} + 2}} = \sqrt{\frac{I_{m}V_{m}}{{Cf}_{s}}\left( {\frac{{\sin \left( {\frac{2\; \pi \; f_{o}}{f_{s}}\left( {N + 1} \right)} \right)}{\sin \left( {\frac{2\; \pi \; f_{o}}{f_{s}}\left( {{2{xN}} - N} \right)} \right)}}{\sin \left( \frac{2\pi \; f_{o}}{f_{s}} \right)} + 1} \right)}} & (50)\end{matrix}$

V_(C,x,2N+2), which is calculated by (50), denotes the peak voltage ofthe x^(th) capacitor. There are

$\frac{f_{s}}{4\; N\; f_{o}}$

number of capacitors, and the capacitor, the peak voltage of which hasthe maximum value, determines the voltage rating of the switches/diodes.According to (50), V_(C,x,2N+2) will be maximum if the followingcondition is valid:

$\begin{matrix}{\frac{d\left( {\sin \left( {\frac{2\pi \; f_{o}}{fs}\left( {{2\; x\; N} - N} \right)} \right)} \right)}{dx} = {\left. 0\Rightarrow{\frac{2\; \pi \; f_{o}}{f_{s}}\left( {{2{xN}} - N} \right)} \right. = {\left. \frac{\pi}{2}\Rightarrow x \right. = {\frac{f_{s}}{8\; N\; f_{o}} + \frac{1}{2}}}}} & (51)\end{matrix}$

The voltage stress of the switches and diodes when

$x = {\frac{f_{s}}{8\; N\; f_{o}} + \frac{1}{2}}$

is equal to:

$\begin{matrix}{V_{C,{MAX}} = {\sqrt{\frac{I_{m}V_{m}}{{Cf}_{s}}\left( {\frac{\sin \left( {\frac{2\; \pi \; f_{o}}{f_{s}}\left( {N + 1} \right)} \right)}{\sin \left( \frac{2\; \pi \; f_{o}}{f_{s}} \right)} + 1} \right)} \cong \sqrt{\frac{I_{m}V_{m}}{{Cf}_{s}}\left( {\frac{\sin \left( {\frac{2\; \pi \; f_{o}}{f_{s}}N} \right)}{\sin \left( \frac{2\; \pi \; f_{o}}{f_{s}} \right)} + 1} \right)}}} & (52)\end{matrix}$

In (52) the voltage stress is expressed based on N. The voltage stresscan also be calculated based on the number of capacitors, M, as follows:

$\begin{matrix}{V_{C,{MAX}} = \sqrt{\frac{I_{m}V_{m}}{{Cf}_{s}}\left( {\frac{\sin \left( \frac{\pi}{2\; M} \right)}{\sin \left( \frac{2\; \pi \; f_{o}}{f_{s}} \right)} + 1} \right)}} & (53) \\{M = \frac{f_{s}}{4\; N\; f_{o}}} & (54)\end{matrix}$

If the maximum allowable capacitance is used, (53) will be simplified asfollows:

$\begin{matrix}{V_{C,{MAX}} = {\sqrt{2} \times \left( {V_{m} + {\sqrt{2}V_{dc}}} \right) \times \sqrt{\frac{\sin \left( \frac{\pi}{2\; M} \right)}{\sin \left( \frac{2\; \pi \; f_{o}}{f_{s}} \right)} + 1}}} & (55)\end{matrix}$

According to (55) increasing the value of M decreases the voltagestress. The maximum value of M, as discussed in previous part is

$\frac{f_{s}}{4\; f_{o}}.$

Assuming

${V_{m} = {200\mspace{20mu} V}},{I_{m} = {10\mspace{14mu} A}},{V_{dc} = {50\mspace{14mu} V}},{I_{dc} = {20\mspace{14mu} A}},{f_{s} = {6\mspace{14mu} {kHz}}},{f_{o} = {60\mspace{14mu} {Hz}}},{\theta_{V} = {- \frac{\pi}{4}}},{\theta_{i} = {- \frac{\pi}{4}}},{C = {2.2\mspace{14mu} \mu \; F}},$

FIG. 25 shows the maximum voltage across the switches/diodes of thisinverter vs. the number of capacitors in the capacitor network.

1.1.3.3 Use of Transformer for Reducing Voltage Stress

Another solution for reducing the voltage stress of the switches anddiodes in the proposed inverter is to use a low frequency transformer atthe load.

By using a transformer, the maximum capacitance can be increased.Assuming the turn ratio of the transformer is “a” (a<1), the maximumrequired capacitance will be determined as follows:

$\begin{matrix}{C < \frac{I_{m}V_{m}}{{f_{s}\left( {{a\; V_{m}\sqrt{2}} + {2V_{dc}}} \right)}^{2}}} & (56)\end{matrix}$

Using (56) and (28) the voltage stress can be determined:

$\begin{matrix}{V_{2,\max} = {\sqrt{\frac{I_{m}V_{m}}{2\; \pi \; f_{in}C}} = {\sqrt{2} \times \left( {{a\; V_{m}} + {\sqrt{2}\; V_{dc}}} \right) \times \sqrt{\frac{f_{s}}{2\; \pi \; f_{o}}}}}} & (57)\end{matrix}$

1.2 Single-Phase ac to Three-Phase ac Capacitive Link Converter

Unlike single-phase ac systems, the instantaneous power of a three-phaseac system (source or load) is a constant dc value. This implies that athree-phase ac to a single-phase ac or a single-phase ac to athree-phase ac converter will have the inherent double frequencyharmonic problem. The single-phase inverter topology described above canbe extended to be used in these systems. FIGS. 26 and 27 depict thebidirectional single-phase ac to three-phase ac converters with seriesand parallel link capacitors, respectively. Referring to FIG. 26, aninput switch bridge 52, output switch bridge 56, and link state 54 areconnected in series. A single phase AC source 51 and three-phase AC load57 are provided. Galvanic isolation, as shown in FIG. 28, can beprovided by adding a high frequency transformer to the link.

1.2.1 Analysis of Single-Phase ac to Three-Phase ac Capacitive LinkConverter

The single-phase ac-to-three phase ac converter has 4 states in eachswitching cycle. If the power flows from a single-phase ac sourcetowards a three-phase ac load, there will be one charging state, twodischarging states, and a state during which no power is transferred.FIG. 29 shows the behavior of the converter with series link capacitorin each of the states. During the time span shown in this figure,I_(in), I_(Ao), and I_(Co) are positive (left to right), and I_(bo) isnegative (right to left). Also, for the case shown in FIG. 29, thevoltage across the output phase pair BCo has the maximum line to lineoutput voltage and it is negative. It is clear that the phase paircarrying the maximum line-to-line voltage and its polarity continuouslychange over a load/source cycle. Also, the polarity of the input andoutput currents change over a load/source cycle.

In state 1, diodes D1 and D4 at the input side and diodes D5 and D8along with switches S6 and S10 at the output-side conduct. The inputcurrent passes the link capacitor and charges it. In state 2, switchesS2 and S4 will be turned on and diodes D8 and D4 stop conducting. Duringthis state, the current of phase C passes the link capacitor, and sinceit is negative the link capacitor starts discharging. To end this stateand initiate state 3, switch S8 is turned on. By turning on switch S8,diode D5 stops conducting, and the current of phase B passes the linkcapacitor. The link capacitor continues discharging. To end this stateswitches S6 and S4 will be tuned off, and diode D9 starts to conduct.During state 4, the link current is zero.

The behavior of the converter with parallel link capacitor is shown inFIG. 30.

The low frequency component of the link capacitor voltage will besimilar to that of the single-phase inverter. Assuming the current andvoltage of the single-phase source/load are:

v _(i)(t)=V _(m) sin(ωt+θ _(V))=V _(m) sin(2πft+θ _(V))   (58)

i _(i)(t)=I _(m) sin(ωt+θ _(I))=I _(m) sin(2πft+θ _(I))   (59)

Two possible equations for low frequency component of the link voltageare as follows:

$\begin{matrix}{{v_{c}(t)} = {{\sqrt{\frac{I_{m}v_{m}}{c\; \omega}}{\sin \left( {{2\pi \; {ft}} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \right)}}}} & (60) \\{{v_{c}(t)} = \sqrt{{\frac{I_{m}V_{m}}{2\; C\; \omega}{\sin \left( {{4\; \pi \; {ft}} + \theta_{V} + \theta_{I}} \right)}} + V_{0}}} & (61)\end{matrix}$

All techniques disclosed herein for reducing the link peak voltage ofthe single-phase inverter topologies can also be used in thesingle-phase ac to three-phase ac topologies. FIGS. 31 and 32 depictthese topologies when a capacitor network is used instead of onecapacitor.

1.3 Single-Phase ac to Single-Phase ac Capacitive Link Inverter

In some embodiment, converters are provided for applications that havesingle-phase ac sources and single-phase ac loads; however, the voltageamplitude and/or frequency of the input and output are not necessarilythe same. The proposed single-phase ac-ac converters are depicted inFIGS. 33 and 34. The isolated configuration is shown in FIG. 35.

In single-phase ac-to-single-phase ac inverters the input and outputpower both have dc and alternating components. The alternatingcomponents of the input and output power are not necessarily the same.Therefore, there may be a mismatch of power that needs to be managed.

The input and output voltages and currents are expressed in (62)-(65):

v _(i)(t)=V _(mi) sin(ω_(i) t+θ _(Vi))=V _(mi) sin(2πf _(i) t+θ _(Vi))  (62)

i _(i)(t)=I _(mi) sin(ω_(i) t+θ _(Ii))=I _(mi) sin(2πf _(i) t+θ _(Ii))  (63)

v _(o)(t)=V _(mo) sin(ω_(o) t+θ _(Vo))=V _(mo) sin(2πf _(o) t+θ _(Vo))  (64)

i _(o)(t)=I _(mo) sin(ω_(o) t+θ _(Io))=I _(mo) sin(2πf _(o) t+θ _(Io))  (65)

Using (62)-(65), the input and output power, will be calculated asfollows:

$\begin{matrix}{{P_{i}(t)} = {{\frac{I_{mi}V_{mi}}{2}\left\{ {{\cos \left( {\theta_{Vi} - \theta_{Ii}} \right)} - {\cos \left( {{2\; \omega_{i}t} + \theta_{Vi} + \theta_{I\; i}} \right)}} \right\}} = {\frac{I_{mi}V_{mi}}{2}\left\{ {{\cos \left\{ {\theta_{Vi} - \theta_{I\; i}} \right)} - {\cos \left( {{4\; \pi \; f_{i}t} + \theta_{V\; i} + \theta_{I\; i}} \right)}} \right\}}}} & (66) \\{{P_{o}(t)} = {{\frac{I_{mo}V_{mo}}{2}\left\{ {{\cos \left( {\theta_{Vo} - \theta_{Io}} \right)} - {\cos \left( {{2\; \omega_{o}t} + \theta_{Vo} + \theta_{I\; o}} \right)}} \right\}} = {\frac{I_{mo}V_{mo}}{2}\left\{ {{\cos \left\{ {\theta_{Vo} - \theta_{I\; o}} \right)} - {\cos \left( {{4\; \pi \; f_{o}t} + \theta_{V\; o} + \theta_{I\; o}} \right)}} \right\}}}} & (67)\end{matrix}$

The average values of input and output power need to be equal:

$\begin{matrix}{{\frac{I_{mi}V_{mi}}{2}{\cos \left( {\theta_{Vi} - \theta_{Ii}} \right)}} = {\frac{I_{m\; o}V_{mo}}{2}{\cos \left( {\theta_{Vo} - \theta_{I\; o}} \right)}}} & (68)\end{matrix}$

The mismatch of input and output power values need to be managed by thelink capacitor. Therefore, the instantaneous value of the link capacitorpower is as follows:

$\begin{matrix}{{P_{c}(t)} = {{\frac{I_{mo}V_{mo}}{2}{\cos \left( {{2\; \omega_{o}t} + \theta_{V\; o} + \theta_{Io}} \right)}} - {\frac{I_{mi}V_{mi}}{2}{\cos \left( {{2\omega_{i}t} + \theta_{V\; i} + \theta_{Ii}} \right)}}}} & (69)\end{matrix}$

Assuming C, i_(c)(t), and v_(c)(t) are the link capacitance and lowfrequency components of the link capacitor current and voltage, thefollowing expression needs to be met:

$\begin{matrix}{{P_{c}(t)} = {{{v_{c}(t)} \times {i_{c}(t)}} = {C \times {v_{c}(t)} \times \frac{d\left( {v_{c}(t)} \right)}{dt}}}} & (70)\end{matrix}$

One of the possible solutions for (69) and (70) is as follows:

$\begin{matrix}{{v_{c}(t)} = {{{\sqrt{\frac{I_{mo}V_{mo}}{C\; \omega_{o}}}{\sin \left( {{\omega_{o}t} + \frac{\theta_{V\; o} + \theta_{I\; o}}{2} + \frac{\pi}{4}} \right)}} - {\sqrt{\frac{I_{m\; i}V_{mi}}{C\; \omega_{i}}}{\sin \left( {{\omega_{i}t} + \frac{\theta_{Vi} + \theta_{Ii}}{2}} \right)}}}}} & (71)\end{matrix}$

Another possible solution for (69) and (70), can be:

$\begin{matrix}{{v_{c}(t)} = \sqrt{{\frac{I_{mo}V_{mo}}{2C\; \omega_{o}}{\sin \left( {{2\omega_{o}t} + \theta_{V\; o} + \theta_{I\; o} + \frac{\pi}{4}} \right)}} - {\frac{I_{m\; i}V_{mi}}{2C\; \omega_{i}}{\sin \left( {{2\omega_{i}t} + \theta_{Vi} + \theta_{Ii}} \right)}} + V_{0}}} & (72)\end{matrix}$

FIG. 36 shows the link voltage for a 10 kW single-phase ac-to-singlephase ac configuration with input and output frequencies of 60 Hz and120 Hz, respectively.

Techniques described herein for reducing the link peak voltage of thesingle-phase inverter topologies can also be used in the single-phase acto single-phase ac topologies. FIGS. 37 and 38 depict these topologieswhen a capacitor network is used instead of one capacitor.

2. Inductive Link Converter 2.1 Inductive-Link Single-Phase ac Inverter

In some embodiments, converters are provided that use an inductor fortransferring the power from input towards output, and also for managingthe mismatch of power between input and output. FIG. 39 shows theschematic of the proposed single-phase inverter. The dc side-current isalways from left to right; however, the voltage can be positive(positive top terminal) or negative (negative top terminal). Positive dcvoltage implies power transfer from dc side towards ac-side; andnegative polarity of dc voltage indicates the power is transferred fromac-side towards the dc-side. Despite providing bidirectional power flow,in most applications that require bidirectional power flow, the polarityof the dc-current needs to be bidirectional rather than the polarity ofthe voltage. To have both positive and negative dc-side currents, aswitch-bridge needs to be used at the dc-side, as shown in FIG. 40.

As depicted in FIGS. 41 and 42, both topologies can provide galvanicisolation through a single-phase high frequency transformer added to thelink.

The disclosed inverter is also capable of interfacing several sourcesand/or loads. A system with two dc sources and a single-phase ac load isshown in FIG. 43.

Similar to the capacitive-link inverter, the inductive-link inverter hasthree states in each cycle. FIG. 44 shows the behavior of the inverterin each state, assuming V_ac is positive. In the first state the inputvoltage (dc source), which is positive, charges the link inductor andresults in an increase of the link inductor current. During this stateswitch S0 and diode D0 conduct. Duration of this state is determinedsuch that the dc-side current meets it reference. During the secondstate, the input-side switch is open and the output side switches/diodesS3, D3, S2, and D2 provide a path for the link current. The voltageacross the link is equal to −V_ac, and its negative polarity results ina decrease of the link inductor current. If V_ac is negative,switches/diodes S1, D1, S4, and D4 are conducting instead of S3, D3, S2,and D2. In both cases, a negative voltage is across the link thatresults in a decrease of the link inductor current. During this statethe link inductor is discharged into the load. Duration of this state isdetermined such that the load current meets its references. In the thirdstate the input and output are disconnected from the link inductor.Switches/diodes S1, D1, S3, and D3 provide a path for link inductorcurrent.

As discussed previously, the dc-side power is constant, and the ac sidepower has a dc component along with an alternating component thefrequency of which is twice the load voltage/current frequency. Themismatch of input and output power needs to be managed by the linkinductor. Assuming the output and input voltages/currents are expressedby (1)-(4), the instantaneous value of link inductor power is asfollows:

$\begin{matrix}{{P_{L}(t)} = {{\frac{I_{m}V_{m}}{2}{\cos \left( {{2\omega \; t} + \theta_{V} + \theta_{I}} \right)}} = {\frac{I_{m}V_{m}}{2}{\cos \left( {{4\; \pi \; f_{o}t} + \theta_{V} + \theta_{I}} \right)}}}} & (73)\end{matrix}$

Assuming L, I_(L)(t), and v_(L)(t) are the link inductance and lowfrequency components of the link inductor current and voltage, thefollowing expression needs to be met:

$\begin{matrix}{{P_{L}(t)} = {{{v_{L}(t)} \times {i_{L}(t)}} = {L \times {i_{L}(t)} \times \frac{d\left( {i_{L}(t)} \right)}{dt}}}} & (74)\end{matrix}$

One of the possible solutions for (73) and (74) is as follows:

$\begin{matrix}{{i_{L}(t)} = {{\sqrt{\frac{I_{m}V_{m}}{L\; \omega}}{\sin \left( {{\omega \; t} + \frac{\theta_{V} + \theta_{I}}{2} + \frac{\pi}{4}} \right)}}}} & (75)\end{matrix}$

Link current is depicted in FIG. 45. The minimum value of the linkinductor current is zero, in this case. Assuming the minimum current ofthe inductor is above zero, another possible solution for (73) and (74)is:

$\begin{matrix}{{i_{L}(t)} = \sqrt{{\frac{I_{m}V_{m}}{2\; L\; \omega}{\sin \left( {{2\omega \; t} + \theta_{V} + \theta_{I}} \right)}} + I_{0}}} & (76)\end{matrix}$

To lower the link peak current, an inductor network can be used insteadof a single inductor, as depicted in FIG. 46.

2.2 Single-Phase ac to Three-Phase ac Inductive Link Converters

In some embodiments, the disclosed topology can be extended to systemswith single-phase ac source (or load) and three-phase ac load (orsource). FIGS. 47 and 48 show the non-isolated and isolatedconfigurations.

This converter can have 4 states in each switching cycle. If the sourceis single-phase ac, and the load is three-phase ac, there is onecharging state, two discharging states, and a state during which nopower is transferred. The principle of the operation of this converterduring each state is shown in FIG. 49. In this figure, it is assumedI_i, I_bo, and I_co are positive, and I_ao is negative. During the firststate, the link inductor is charged through the source. During thesecond and third states output phase pairs ab_o and ac_o discharge thelink inductor, respectively. During the fourth state the link inductoris shorted.

An inductor network can be used instead of the link inductor to reducethe maximum peak of inductor current, as shown in FIG. 50.

2.3 Single-Phase ac to Single-Phase ac Inductive Link Converter

FIGS. 51 and 52 depict the non-isolated and isolated single-phase ac-acinverters. The single-phase ac to single phase ac converter withinductor network is shown in FIG. 53.

In some embodiments, the switching device(s) of the input circuitry andthe output switch bridge can be a field effect transistor (FET), aninsulated gate bipolar transistor (IGBT), or a metal-oxide-semiconductorfield-effect transistor (MOSFET). In some embodiments, a switchingdevice can be a field effect transistor (FET), an insulated gate bipolartransistor (IGBT), or a metal-oxide-semiconductor field-effecttransistor (MOSFET) with an associated diode. In some embodiments, aswitching device can be a field effect transistor (FET), an insulatedgate bipolar transistor (IGBT), or a metal-oxide-semiconductorfield-effect transistor (MOSFET) with anti-parallel diode.

As used herein, a controllable device may be a device that can becontrolled to act as a switch, such that the device conducts currentwhen switched on and does not conduct current when switched off. In somecases, a controllable device may have three or more terminals, with oneof the terminals corresponding to an input that may allow or prevent theflow of current through two other terminals. In some embodiments,controllable device may include a bipolar junction transistor or a fieldeffect transistor, among other components. An uncontrollable device maybe a device that, unlike a controllable device, does not include aterminal input that controls the flow of current through the device. Insome cases, an uncontrollable device may have two or more terminals,with current flowing from one terminal through the other. Anuncontrollable device may only conduct in one direction and prevent theflow of current in the opposite direction; this property of anuncontrollable device may be referred to herein as “reverse-blocking” ofsuch a device. Such an uncontrollable device may start to conduct when apositive voltage is applied across it, and when it conducts the voltageacross it remains zero. In some embodiments, the uncontrollable devicemay include a diode, among other components. Some uncontrollable devicesmay turn off when the current flowing through it becomes zero. It shouldbe noted that a controllable device may also include an uncontrollabledevice, such that the device's conduction may be controllable in onedirection and it is uncontrollable in another direction.

In some embodiments, the reactive component can be at least onecapacitive device operative at a capacitance of less than 1 mF, lessthan 1 μF, or less than 1 nF. Film capacitors can have an operativerange of about 1×10⁻⁴ F to less than 1×10⁻⁹ F. Electrolytic capacitorscan have an operating range of about 1×10⁻⁷ F to about 1 F.

The power conversion devices may be controlled in any suitable manner,such as by circuitry or by a controller having one or more processors,memory, and machine-readable instructions stored in the memory that,upon execution by the one or more processors, cause the device to carryout operations to control sequence and duration of each of thecontrollable devices.

As used herein, “consisting essentially of” allows the inclusion ofmaterials or steps that do not materially affect the basic and novelcharacteristics of the claim. Any recitation herein of the term“comprising,” particularly in a description of components of acomposition or in a description of elements of a device, can beexchanged with “consisting essentially of” or “consisting of.”

It will be appreciated that the various features of the embodimentsdescribed herein can be combined in a variety of ways. For example, afeature described in conjunction with one embodiment may be included inanother embodiment even if not explicitly described in conjunction withthat embodiment.

To the extent that the appended claims have been drafted withoutmultiple dependencies, this has been done only to accommodate formalrequirements in jurisdictions which do not allow such multipledependencies. It should be noted that all possible combinations offeatures which would be implied by rendering the claims multiplydependent are explicitly envisaged and should be considered part of theinvention.

The present invention has been described in conjunction with certainpreferred embodiments. It is to be understood that the invention is notlimited to the exact details of construction, operation, exact materialsor embodiments shown and described, and that various modifications,substitutions of equivalents, alterations to the compositions, and otherchanges to the embodiments disclosed herein will be apparent to one ofskill in the art.

What is claimed is:
 1. A power conversion device comprising: input circuitry configured to be coupled to a power source or load, the input circuitry comprising at least one switching device or diode; an output switch bridge configured to be coupled to a load or power source, the output switch bridge comprising at least four controllable switching devices arranged in a bridge configuration to control current output; and a link stage comprising at least one reactive component configured for alternating current (AC) operation, wherein the input circuitry, output switch bridge and link stage are operative to regulate input and output currents and manage power mismatch between the power source and load.
 2. The power conversion device of claim 1, wherein the device is operative to suppress a double frequency harmonic component at the input circuitry.
 3. The device of claim 1, wherein switches in the input circuitry and output switch bridge are operative at a fixed switching frequency.
 4. The device of claim 1, wherein the device is operative to control the input current to be about equal to a selected reference value.
 5. The device of claim 1, wherein the input circuitry comprises an input switch bridge configured to be coupled to a direct current (DC) power source, the input switch bridge comprising at least one switching device controllable to regulate an input DC current with suppression of a double frequency harmonic component.
 6. The device of claim 1, wherein the output switch bridge is configured to be coupled to an AC load, the output switch bridge comprising at least four controllable switching devices arranged in a bridge configuration to control current output to the load.
 7. The device of claim 1, wherein the device is operative as a single phase inverter or rectifier.
 8. The device of claim 1, wherein the device is operative to regulate the input current and the output current simultaneously.
 9. The device of claim 1, wherein the link stage is arranged in series or in parallel with the input switch bridge and the output switch bridge.
 10. The device of claim 1, wherein the reactive component comprises a film capacitor, a ceramic capacitor, an electrolytic capacitor, or an inductive device.
 11. The device of claim 1, wherein the device is operative to provide bidirectional flow of power.
 12. The device of claim 1, wherein each of the switching devices of the output switch bridge comprises a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), or a metal-oxide-semiconductor field-effect transistor (MOSFET) with anti-parallel diode; and/or wherein the at least one the switching device of the input circuitry comprises a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), or a metal-oxide-semiconductor field-effect transistor (MOSFET) with anti-parallel diode.
 13. The device of claim 1, further comprising circuitry that causes, and/or a controller comprising one or more processors, memory, and machine-readable instructions stored in the memory that, upon execution by the one or more processors, cause the device to carry out operations to control sequence and duration of each of the controllable switching devices.
 14. The device of claim 1, wherein the device is operative in at least three states, including at least one state to charge the reactive component of the link stage from the power sources and through the input switch bridge, at least one state in which power is discharged from the link stage into the loads through the output switch bridge, and at least one state in which no power is transferred through the link stage.
 15. The power conversion device of claim 1, wherein a voltage rating of the switching devices is about equal to a maximum link stage voltage.
 16. The power conversion device of claim 1, wherein a maximum voltage of the link stage is selected based on a selected maximum link stage capacitance.
 17. The power conversion device of claim 1, wherein the link stage comprises a plurality of capacitors, each capacitor in series with a bidirectional conducting bidirectional blocking controllable switching device, the plurality of capacitors arranged in series or in parallel with the input circuitry and the output switch bridge, and wherein each capacitor transfers power in at least two switching cycles over a load power cycle.
 18. The power conversion device of claim 1, wherein the link stage comprises a plurality of series inductors, each inductor in parallel with a forward conducting bidirectional blocking controllable switching device, the plurality of inductors arranged in series or in parallel with the input circuitry and the output switch bridge.
 19. A method of controlling a power conversion device, comprising: providing the power conversion device of claim 1; and operating the device to regulate the input and output currents with suppression of a double frequency harmonic component.
 20. A method of controlling a power conversion device, comprising: providing the power conversion device of claim 1; and operating the device with a plurality of switching cycles, each switching cycle comprising at least one charging state, at least one discharging state, and at least one state during which no power is transferred. 